Systems and methods for manufacturing nano-electro-mechanical-system probes

ABSTRACT

A method for implementing a transistor using multiple integrated probe tips is provided. The method comprises the steps of (1) providing a sample; (2) providing a microscope probe comprising a plurality of probe tips; (3) contacting a first outer probe tip of the plurality of probe tips to the sample, wherein he first outer probe tip is configured to act as a source terminal for a transistor; (4) contacting a second outer probe tip of the plurality of probe tips to the sample, wherein the second outer probe tip is configured to act as a drain terminal for the transistor; (5) using an inner probe tip of the plurality of probe tips as a gate terminal for the transistor; and (6) characterizing the sample with the plurality of probe tips.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation Application of U.S. patent application Ser. No. 17/445,448, filed on Aug.t 19, 2021, which application claims priority to U.S. patent application Ser. No. 16/751,913, filed on Jan. 24, 2020, now U.S. Pat. No. 11,125,774, which application claims priority to U.S. patent application Ser. No. 16/553,968, filed on Aug. 28, 2019, now U.S. Pat. No. 10,545,171, which application claims priority to U.S. patent application Ser. No. 15/054,626, filed on Feb. 26, 2016, now U.S. Pat. No. 10,436,814, which application claims priority to U.S. Provisional Patent Application Ser. No. 62/121,208, filed on Feb. 26, 2015, entitled “Systems and Methods for Manufacturing Nano-Electric-Mechanical-System Probes,” the entire disclosures of which are incorporated herein by reference in their entireties.

FIELD OF THE INVENTION

The present disclosure is directed generally to systems and methods for manufacturing multiple integrated tip probes for scanning probe microscopy.

BACKGROUND

In order to achieve low-powered high-performance electronics, the size of transistors forming the building block of very large scale integrated (VLSI) circuits are drastically decreasing. However, tool resolution and sensitivity continue to be major challenges in semiconductor device fault isolation and analysis. As transistors continue to scale down to 10 nm nodes and beyond, well-known optical microscopy techniques no longer work due to wavelength limitations. For instance, conventional failure analysis methods involve the use of Focused Ion Beam (FIB) deposited pads or Scanning Electron Microscope (SEM). However, minute charge currents from the FIB and SEM adversely affect measured results. The induced charge from the FIB and SEM can even break the ultra-thin transistor tunneling gate oxide layer. In addition to this, Passive Voltage Contrast (PVC) techniques lack the sensitivity to identify faulty vias and contacts.

Single-tip Scanning Probe Microscopy, such as Atomic Force Probing (AFP) and Atomic Force Microscopy (AFM), is a powerful tool for non-destructive determination of root causes of IC chip failure, including extension to the sub 10 nm node regimes. However, AFM effectiveness is severely limited by its single tip design. As a result, a range of fundamental phenomena that exist in thin film materials and devices are inaccessible. As just one example, the effects of dislocations and grain boundaries in thin films cannot be characterized, as the ability to perform trans-conductance (conduction between two tips) measurements at the nanoscale is a critical gap. Trans-conductance would enable a richer understanding of how electrons transport and interact with their surroundings by offering insight into the local density of states, tip-sample coupling, transport mechanisms, scattering phase shifts and inelastic free mean paths of electrons.

Multiple-tips SPMs have been proposed as a way of overcoming the inherent limitations of the single-tip SPM. However, there have been significant challenges to engineering a suitable multiple-tips SPM. Previous approaches to a multiple-tip SPM have relied on independent macroscopically-fabricated probes. These platforms are complex, difficult to actuate, and have limited scale-down. They are also prohibitively expensive to manufacture.

Accordingly, there is a continued need in the art for multiple-tips SPMs that are both cost-effective and easily manufactured and functionalized to the specific investigation for which they will be utilized. Also needed are efficient and cost-effective methods of manufacturing multiple integrated tip probes.

SUMMARY OF THE INVENTION

The present disclosure is directed to systems and methods for manufacturing multiple integrated tip (MiT) probes for scanning probe microscopy. The MiT probe is a Nano-Electro-Mechanical System (NEMS) that integrates mechanical and electrical functionality in a monolithically-fabricated nano-structure which is tailored and functionalized to the specific investigation. The MiT scanning probe microscope provides two or more monolithically integrated cantilever tips that can be placed within nanometers of each other, with monolithically integrated transistors to amplify signals. As a result, the MiT SPM is able to perform atomic force microscopy without the need for laser tip alignment. Further, the MiT SPM is capable of nanoprobing surfaces where at least two of the integrated tips are in direct contact or in close proximity with the sample.

Generally, in one aspect, a method for implementing a transistor using multiple integrated probe tips is provided. The method comprising the step of providing a sample.

The method further comprises the step of providing a microscope probe comprising a plurality of probe tips.

The method further comprises the step of contacting a first outer probe tip of the plurality of probe tips to the sample. The first outer probe tip is configured to act as a source terminal for a transistor.

The method further comprises the step of contacting a second outer probe tip of the plurality of probe tips to the sample. The second outer probe tip is configured to act as a drain terminal for the transistor.

The method further comprises the step of using an inner probe tip of the plurality of probe tips as a gate terminal for the transistor.

The method further comprises the step of characterizing the sample with the plurality of probe tips.

According to an example, the inner probe tip makes soft contact with the sample.

According to an example, the inner probe tip is in proximity to the sample.

According to an example, the inner probe tip comprises a dielectric coating. The dielectric coating is in contact with the sample.

According to an example, the inner probe tip comprises a few nanometers of either high or low-k dielectric that is deposited at an apex of the inner probe tip.

According to an example, the inner probe tip comprises a dielectric coating, and further wherein the dielectric coating is in proximity to the sample.

According to an example, the sample comprises a 2D material. The 2D material may be graphene or molybdenum disulphide.

According to an example, the sample comprises silicon substrate or gallium nitride.

According to an example, the plurality of probe tips is used to perform output and transfer curves of the transistor.

According to an example, the inner probe tip is configured to be shorter than both the first outer probe tip and the second outer probe tip. Further to this example, there may be an airgap or a gate capacitance between the inner probe tip and the sample. The gate capacitance may be varied by applying voltages to an actuation electrode that causes the inner probe to extend towards or retract from the sample.

These and other aspects of the invention will be apparent from the embodiment(s) described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more fully understood and appreciated by reading the following Detailed Description in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic representation of a Butterworth-Van Dyke equivalent circuit for a NEMS resonator, in accordance with an embodiment.

FIG. 2 is schematic representation of a circuit depicting parallel connection of a compensation capacitor (Static) to a resonator, resulting in parasitic feedthrough self-cancelation, in accordance with an embodiment.

FIG. 3 is a schematic representation of a MiT probe with a compensation device structured identically to the resonator, in accordance with an embodiment.

FIG. 4 is a schematic representation of a MiT probe with on-chip feedthrough cancellation using monolithically integrated static and resonating structures, in accordance with an embodiment.

FIG. 5 is a SEM scanning electron microscope (SEM) image of a MiT probe with gold probe tips, in accordance with an embodiment.

FIG. 6 is a SEM image of a MiT probe with MoSi₂ probe tips, in accordance with an embodiment.

FIG. 7 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 8 is a SEM image of a MiT probe with a platinum metal layer that sits on a silicon supporting structure, in accordance with an embodiment.

FIG. 9 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 10 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 11 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 12 is a top view schematic of a MiT probe with three degrees of freedom, in accordance with an embodiment.

FIG. 13 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 14 is a top view schematic representation of a MiT probe with three degrees of freedom, in accordance with an embodiment.

FIG. 15 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 16 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 17 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 18 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 19 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 20 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 21 is a schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 22 is a schematic representation of a MiT probe where the middle probe tip represents a gate and the side probe tips are source and drain terminals of a transistor, in accordance with an embodiment.

FIG. 23 is a top view schematic representation of a MiT probe, in accordance with an embodiment.

FIG. 24 is a schematic representation of a probe tip of a MiT probe where the middle probe tip is shorter than the side probe tips, in accordance with an embodiment.

FIG. 25 is a schematic representation of a probe tip of a MiT probe where the middle probe tip is shorter than the side tips, in accordance with an embodiment.

FIG. 26 is a schematic representation of a probe tip of a MiT probe where a high or low-k dielectric is deposited at the apex of the middle probe tip, in accordance with an embodiment.

FIG. 27 is a schematic representation of resistors which can be implemented with an MiT probe, in accordance with an embodiment.

FIG. 28 is a schematic representation of a variable resistor which can be implemented with an MiT probe, in accordance with an embodiment.

FIG. 29 is a schematic representation of a common source amplifier which can be implemented with a MiT probe, in accordance with an embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

The present disclosure includes various embodiments of a system and method for manufacturing multiple integrated tips (MiT) probes for use with a scanning probe microscope (SPM) system. The MiT-SPM enables nanoscale atomic imaging, electrical probing of trans-conductance, and parametric analysis of a transistor, among many other aspects.

Capacitive coupling and low signal-to-noise ratio leads to passive Nano-Electro-Mechanical-System (NEMS) devices generally having lower performance. FIG. 1 shows the small signal electrical equivalent circuit of a NEMS resonator structure. The resonator can be modeled as a typical Butterworth-Van Dyke equivalent circuit where L_(x), C_(x), and R_(x) represent the motional inductance, capacitance and resistance respectively. C₀ is the parasitic DC capacitance of the resonator and C_(p) represents the total parasitic capacitance introduced from the wirebonds, circuit board and packaging. If C₀ and C_(p) are large, they will generate large amounts of current that will obscure the motional current of the resonator. The current from the input (V_(in)) to the output of the NEMS resonator has three main paths:

I_(f) =I _(co) +I _(x) +I _(cp)   (Eq. 1)

The admittance of the NEMS resonator is given by the following equation:

$\begin{matrix} {Y = {{SC}_{0} + \frac{{SC}_{X}}{{S^{2}L_{X}C_{X}} + {SR_{X}C_{X}} + 1} + {SC}_{p}}} & \left( {{Eq}.2} \right) \end{matrix}$

From Equation 2, if the feedback capacitor C_(o) and parasitic capacitor C_(p) increases, their effective impedance decreases and would sink most of the input current thus masking the motional current I_(x) which is the parameter of interest. To minimize the effect of C₀ and C_(p), either an on-board or off-board compensating capacitor can be added in parallel to cancel their effect. FIG. 2 illustrates the parallel connection of the compensation capacitor (Static) to the resonator. The compensation capacitor is fixed to the substrate so does not generate motional current. The current from the Static structure (I_(co)+I_(cp)) is inverted into I_(comp). I_(comp) is electrically combined with the current from the resonator I_(f). I_(total) is fed into an off board transimpedance amplifier.

I _(comp)=−(I _(co) +I _(cp))   (Eq. 3)

I _(Total) =I _(f) +I _(comp) =I _(x)   (Eq. 4)

The compensation device is structurally identical to the resonator as shown in FIG. 3 . The comb-drives that form the static component 112 in FIG. 3 are fixed where as those that form the resonator component 114 are fully released from the substrate and capable of vibrating. Both AC and DC voltages are applied to electrode A2. The parasitic current (I_(co)+I_(cp)) through the static component is inverted by on-board inverter into I_(comp) which is then combined with the resonator current I_(f). The combined current is fed into a transimpedance amplifier. The probe tip device depicted in FIG. 3 has both a static component 112 and a resonating component 114. The static structures are fixed on the substrate whereas the resonating structures are free to mechanically move and can be excited in a vibrational mode.

The probe tip can be used to image surfaces in both AFM and Scanning Tunneling Microscopy (STM) modes. In contact mode AFM, the tip is dragged across the surface of a sample. As the tip encounters different roughness of the surface, since the tip is supported by springs, it moves up and down. This up and down movement of the tip can be sensed by the differential capacitors B1 and B2. The device is biased as shown in FIG. 4 , where AC voltages are applied to B1 and B2 and DC voltage applied to the probe tip. STM images can also be acquired with the biased probe tip.

V_(SENSE) changes with the displacement of the probe tip and its value can be used to create a 3D topographical image of the surface. For small probe tip displacement the following equation is utilized:

$\begin{matrix} {V_{SENSE} = {V_{IN}\left( \frac{y}{y_{0}} \right)}} & \left( {{Eq}.5} \right) \end{matrix}$

where y is a small displacement caused by the probe tip in contact with a surface and y_(o) is the default smallest gap between any of the fingers on B1 or B2 and a probe tip finger.

EXAMPLE 1 Fabrication of All-Metal Probe Tips with Differential Sensing Capacitors and Feedback Cancellation Structure

To ensure that there is good ohmics between the probe tip and the sample, the workfunction of the probe tip and sample should be closely matched. In most semiconductor technology nodes, tungsten plugs are used to connect a metal to the source, drain, and gate regions of the transistor. To probe these plugs, tungsten probe tips are usually used due to its hardness and high conductivity. But the tungsten probes are susceptible to oxidation which in effect render them insulating and non-ideal for electrical probing. Both chemical and mechanical techniques are used to remove the oxide on the probe tip.

Other structures with different workfunctions would require different conducting probe tip materials. Platinum and gold are metals of interest for nanoprobing due to their high conductivity and non-oxidation tendencies. Gold is pretty soft and might stick to surfaces. To this end, probe tip devices with different conducting materials or metals have been fabricated as shown in the SEM image in FIGS. 5 and 6 . Table 1, in accordance with an embodiment, provides a method for the nanofabrication of an all-metal integrated probe tip device. Referring to FIG. 7 is an image of the finalized probe device according to the method of Table 1.

TABLE 1 Method for Nanofabrication of All- Metal Integrated Probe Tip Device Step # Process 100 A Double Sided Polished (DSP) silicon wafer is provided. 102 SiO₂ is deposited via Plasma Enhanced Chemical Vapor Deposition (PECVD) on both the front side and backside of the wafer. Approximately 2 μm of SiO₂ is deposited, although other amounts are possible. 104 Chromium is sputtered as an adhesion layer, followed by sputtering a metal of choice, including but not limited to gold, MoSi₂, Pt, and other metals. 106 The photoresist is then spun, patterned, and developed. 108 The metal is dry etched with, for example, either ion mill or Cl₂ chemistry. 110 Strip resist. 112 Spin resist on backside of wafer and pattern it, and then develop the resist. 114 Use the resist as an etch mask to etch the backside SiO₂ layer. 116 Use the backside SiO₂ layer as an etch mask to etch the bulk Si wafer to the front side oxide layer. 118 Use either vapor Hydrofluoric Acid (HF) or Buffered Oxide Etch (BOE) to etch both the front side and backside SiO₂ layers. The probe device is fully released at this stage.

EXAMPLE 2 Fabrication of Probe Tip Device with Metal Overhang, Parasitic Feedthrough Self-Cancelation and Differential Sensing Capacitors

The stress gradient in the metal films might bend the probe tip either upwards or downward. To mitigate the effect of stress gradient, the metal can be mechanically attached to a supporting material.

According to an embodiment, FIGS. 8, 9, and 10 , for example, show a metal terminal probe end 80 of a probe tip which sits on, is supported by, or is affixed to, a silicon supporting layer 82. The metal probe tip 80 extends past the silicon support layer 82 and during AFM/STM imaging and nanoprobing, only the metal probe tip 80 is in contact with the sample. The metal of choice is not limited to platinum, but gold and other conductive materials can also be utilized. Also, various materials such as silicon dioxide, silicon nitride can be used for the structural support layer. As illustrated in FIG. 9 , silicon support layer 82 is in contact with at least one spacer S arranged to lift silicon support layer 82 off of the substrate creating a visible air-gap. The platinum tip can be used for both AFM/STM imaging and nanoprobing. An embodiment of the nanofabrication method for the metal-overhang probe tip is outlined in Table 2.

TABLE 2 Method for Nanofabrication of a Probe Device with an Extended Conductive Material/Metal Over-Hang Step # Process 200 A Double Sided Polished (DSP) silicon wafer is provided. 202 Perform PECVD deposition of 2 μm SiO₂ on the handle layer (back side of SOI wafer). 204 Sputter chromium, such as a few nanometers, as an adhesion layer followed by the sputtering of metal, such as platinum (Pt) on the front side of wafer. 206 Spin negative tone photoresist on the Pt layer. 208 Lithographically pattern the probe tip device, and then develop the resist. 210 Ion mill the Pt and Cr layers, then use Deep Reactive Ion Etching (DRIE) to etch the Si device layer. 212 Strip the photoresist. 214 Process the SOI handle layer by patterning the oxide etch mask. Spin resist, pattern, and develop. 216 Use CHF₃/O₂ chemistry to dry etch the oxide layer. 218 Spin positive tone resist on the SOI device layer. 220 Expose a few μm or nm of the tip of the probe. 222 Etching the silicon material below the exposed Pt layer. 224 Strip the resist. 226 Use the SiO₂ layer as an etch masks to DRIE the handle layer and terminate on the BOX. 228 Use either vapor HF or Buffered Oxide Etch (BOE) to etch the SiO₂ backside etch mask and BOX. The probe device is fully released at this stage.

The support layer for the metal is not limited to silicon but other materials such as silicon dioxide, silicon nitride, and MoSi₂, among others. Two or more individual probe tips can be synchronously and simultaneously used to perform AFM or STM imaging of a sample. Using the acquired image, individual tips can be navigated to specific points on the sample. For example, the plugs in an Integrated Circuit (IC) can be nanoprobed using the device, where all the four individual probe tips are scanned simultaneously to acquire STM or AFM image and subsequently navigated to specific plugs for nanoprobing. The 3D image can then be used as feedback for positioning each tip at a particular point on the sample.

According to an embodiment using the fabrication process outlined in Table 2 above, curved probe tips can be realized as shown in FIG. 10 . These tips could have integrated deflection electrodes that can actuate and sense the probe tip in resonance as well as integrated differential capacitive sensors for sensing the motion of the probe tip device. Two or more of these curved tips can be synchronized and used to perform Atomic Force Probing of a device.

According to an embodiment using the fabrication process outlined in Table 2, pre-defined shaped single tips with extended metal overhangs can be realized. These probe tips can be used as fabricated, or soldered to metal shank, and inserted into manipulators. If the SOI device layer is thick, then the buried oxide layer can be fully etched away to release probe tips.

EXAMPLE 3 Fabrication of Monolithically Integrated Probe Tips with Interdigitated Structures Between Two or More Probe Tips

Freely released and suspended multiple integrated tips tend to pull-in to each other after the release process or during nanoprobing. To mitigate the pull-in effect, interdigitated structures can be monolithically inserted between the probes. Table 3 below illustrates the fabrication process for monolithically implementing the interdigitated structures, in accordance with an embodiment. Referring to FIG. 11 is an image of the finalized probe device according to the method of Table 3. In FIG. 11 , for example, the probe includes a structure 90 with interdigitated structures 92 positioned between and on the outer side of the probe tips 94.

TABLE 1 Method for Implementing Monolithically Interdigitated Structures Between Probe Tips. Step # Process 300 Start with an SOI wafer. 2 μm device layer and 2 μm buried oxide (BOX) layer. 302 PECVD deposition of 2 μm SiO₂ on the handle layer (backside of SOI wafer). 304 Sputter a few nanometers of Cr as an adhesion layer followed by sputtering a metal of choice, such as gold, MoSi₂, Pt, and others. 306 Spin negative tone photoresist on the metal layer. 308 Lithographically pattern the probe tip device. Develop the resist. 310 Ion mill the Pt and Cr layers. Then use DRIE to etch the Si device layer. 312 Strip the photoresist. 314 Process the SOI handle layer by patterning the SiO₂ etch mask. Spin resist, pattern and develop. 316 Use CHF₃/O₂ chemistry to dry etch the oxide layer. Strip the resist. 318 Deposit a few nanometers of conformal SiO₂ by Atomic Layer Deposition (ALD). Then deposit another layer of conformal undoped Si (polysilicon or amorphous). Spray coat photoresist, pattern and etch undoped Si and SiO₂ layers. The probes tips are sandwiched in SiO₂ and Si interdigitated structures. 320 Spray coat photoresist on the SOI device layer. 322 Expose a few μm or nm of the tip of the probe device. 324 Etch the silicon material below the exposed Pt layer. 326 Strip the resist. 328 Use the SiO₂ layer as an etch masks to DRIE the handle layer and terminate on the BOX. 330 Use either vapor HF or Buffered Oxide Etch (BOE) to etch the SiO₂ etch mask and BOX layer. The SiO₂ layers surrounding the interdigitated structures are also removed with vapor HF or BOE. The probe device is fully released at this stage.

The 4-tip MiT probe can be considered as a Ground-Signal-Ground Signal (GSGS) probe device where two signals that are out-of- phase can be introduced on the Signal probes and shielded by the Ground probes. Bottom electrodes can also be placed below each probe tip for controlled downward deflection of each probe tip. The tips can be used for conventional 4-point probing. Also, the 4 probes can be scanned across a sample surface and the current between any of the two tips can be used for imaging the surface.

EXAMPLE 4 Fabrication of Monolithically Integrated Probe Tips with Bottom Actuation Electrodes

Certain STM/AFM imaging and nanoprobing require that probe tips exhibit 3 Degrees of Freedom (DOF). FIG. 12 is the top view of a monolithically integrated tips device with 3 DOF. Applied voltages to electrode A2 move the middle probe tip in-plane whereas applied voltages to electrodes C1 or C2 laterally deflects the middle probe tip. Electrode E3 runs below the middle probe tip and applied voltages to E3 bends down the middle probe tip towards the substrate. The side probe tips also have electrodes E1 and E2 that bend down the tips when actuated. Table 4 illustrates the fabrication of MiT probe with 3 DOF where the bottom electrodes (E1, E2 and E3) are used to deflect the probe tips out of plane. Referring to FIG. 13 is an image of the finalized probe device according to the method of Table 4.

TABLE 4 Fabrication of MiT Probe With 3 DOF. Step # Process 400 Start with undoped Double Sided Polished (DSP) silicon wafer. 402 Deposit 2 μm of PECVD SiO₂ on one side of the DSP polished wafer. 404 Pattern the SiO₂ layer with photoresist then etch the SiO₂ layer. 406 Strip the photoresist 408 Spin resist on frontside of the wafer. 410 Pattern the bottom actuation electrodes. 412 Using the resist as an etch mask, etch about 500 nm into the silicon wafer. Strip resist. 414 Sputter about 1 μm of 1^(st) metal layer to fill-in the etched trenches. 416 Perform Chemical Mechanical Polishing (CMP) to planarize the wafer surface. The bottom electrodes are embedded into the silicon wafer. 418 Deposit 2 μm of PECVD SiO₂ on the frontside of the wafer. 420 Deposit highly doped polysilicon, amorphous silicon or MoSi₂ onto the frontside SiO₂ layer. 422 Sputter a few nanometers of Cr to serve as adhesion layer followed by sputtering of 2^(nd) metal layer. 424 Spin resist, pattern, and develop the photoresist. Ion mill the Cr and 2^(nd) metal layer and use DRIE to etch the polysilicon layer. 426 Strip resist. 428 Spray resist and pattern a region to expose the tips. 430 Etch the silicon material below the exposed Pt layer. 432 Strip resist. 434 Process the backside of the wafer by DRIE the wafer using the backside SiO₂ layer. 436 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both the frontside and backside SiO₂ layers. The probe device is fully released at this stage.

The bottom electrodes are used to deflect the probes out-of-plane. The metal choice for the actuation electrodes (1^(st) metal layer) and the probe tips (2^(nd) metal layer) could be the same or different. The 3-Tip MiT probe configuration allows these probes to be used as Ground-Signal-Ground (GSG) RF/microwave probes for testing microwave and RF circuits. The 3-Tip MiT probe can also be used for AFP. Using the fabrication process outlined in Table 4 above, a 5-point probe device can be realized. The middle probe tip is used for AFM/STM imaging then it is retracted and the remaining 4 probe tips are used for conventional 4-point probe measurements.

EXAMPLE 5 Fabrication of Monolithically Integrated Probe Tips with Bottom and Side Actuation Electrodes

According to an embodiment is the fabrication of monolithically integrated probe tips with bottom and side actuation electrodes, where the side tips are laterally deflected. The side probe tips can be independently controlled by applying voltages to electrodes E1 and E2 (bottom electrodes) and F1 and F2 (side electrodes) as shown in FIG. 14 . Illustrated in Table 5 below is the fabrication of an MiT probe with 3 DOF where the bottom electrodes (E1, E2 and E3) are used to deflect the probe tips out-of-plane. F1 and F2 are independently used to laterally deflect the side tips. Referring to FIG. 15 is an image of the finalized probe device according to the method of Table 5.

TABLE 5 Fabrication of MiT Probe with 3 DOF and Side Actuation Electrodes. Step # Process 500 Start with undoped DSP silicon wafer. 502 Deposit 2 μm of PECVD SiO₂ on one side of the DSP polished wafer. 504 Pattern the SiO₂ layer with photoresist then etch the SiO₂ layer. 506 Strip the photoresist. 508 Spin resist on frontside of the wafer. 510 Pattern the bottom actuation electrodes. 512 Using the resist as an etch mask, etch about 500 nm into the silicon wafer. Strip resist. 514 Sputter about 1 μm of 1^(st) metal layer to fill-in the etched trenches. 516 Perform CMP to planarize the wafer surface. The bottom electrodes are embedded into the silicon wafer. 518 Deposit 2 μm of PECVD SiO₂ on the frontside of the wafer. 520 Deposit highly doped polysilicon, amorphous silicon or MoSi₂ onto the frontside SiO₂ layer. 522 Sputter a few nanometers of Cr to serve as adhesion layer followed by sputtering of 2^(nd) metal layer. 524 Spin resist, pattern, and develop the photoresist. Ion mill the Cr and 2^(nd) metal layer and use DRIE to etch the polysilicon layer. 526 Strip resist. 528 Spray coat resist and pattern a region to expose the tips. 530 Etch the silicon material below the exposed Pt layer. 532 Strip resist. 534 Process the backside of the wafer by DRIE the wafer using the backside SiO₂ layer. 536 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both the frontside and backside SiO₂ layers. The probe device is fully released at this stage.

EXAMPLE 6 Fabrication of Monolithically Integrated Probe Tips with Top and Bottom Actuation Electrodes

In certain applications, the middle probe tip might be required to be deflected both down (towards the substrate) and up (away from the substrate). Table 6 illustrates the fabrication process steps in realizing such a device. The metal choice for the actuation electrodes (1^(st) metal) and the probe tips (2^(nd) metal) could be the same or different. Referring to FIG. 16 is an image of the finalized probe device according to the method of Table 6, where the middle probe tip can deflect both up and down with respect to the substrate.

TABLE 6 Fabrication Process for Making MiT Probe with 3 DOF. Step # Process 600 Start with an undoped DSP silicon wafer. 602 Deposit 2 μm of PECVD SiO₂ on one side of the DSP polished wafer. 604 Pattern the SiO₂ layer with photoresist then etch the SiO₂ layer. 606 Strip the photoresist 608 Spin resist on frontside of the wafer. 610 Pattern the bottom actuation electrodes. 612 Using the resist as an etch mask, etch about 500 nm into the silicon wafer. Strip resist. 614 Sputter about 1 μm of 1^(st) metal to fill-in the etched trenches. 616 Perform CMP to planarize the wafer surface. The bottom electrode is embedded into the silicon wafer. 618 Deposit 2 μm of PECVD SiO₂ on the frontside of the wafer. 620 Deposit highly doped polysilicon, amorphous silicon or MoSi₂ onto the frontside SiO₂ layer. 622 Sputter a few nanometers of Cr to serve as adhesion layer followed by sputtering of 2^(nd) metal. 624 Spin resist, pattern, and develop the photoresist. Ion mill the Cr and 2^(nd) metal layer and use DRIE to etch the polysilicon layer. 626 Strip resist 628 Deposit PECVD SiO₂ and planarize by CMP. Next, deposit undoped polysilicon or undoped amorphous silicon. Spin resist and pattern the silicon top bridge. Etch the pattern into the undoped polysilicon or amorphous silicon layer. Strip resist. 630 Sputter top metal layer. Spin resist and pattern the top metal layer. Use the resist as an etch mask and use the ion mill to etch the metal layer. 632 Spin and pattern the photoresist. 634 Pattern the resist and etch the SiO₂ layer to expose the probe tips. Etch the silicon material below the exposed Pt layer. 636 Strip resist. 638 Use the backside SiO₂ layer as DRIE etch mask to etch the wafer. 640 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both the frontside and backside SiO₂ layers. The probe device is fully released at this stage. The top electrode is suspended above the middle probe tip.

EXAMPLE 7 Fabrication of Monolithically Integrated Self-Aligned Stacked Probe Devices

Several MiT probes can be monolithically vertically integrated to offer several probe tips that can be used to probe structures on a wafer. Table 7 illustrates the fabrication process for the vertically stacked MiT probes. The metal choice used in the MiT probe stack could be the same (1^(st) metal is the same as 2^(nd) metal) or different (1^(st) metal is different from 2^(nd) metal). The MiT probe stack is not limited to two layers but several layers can also be implemented using the outlined fabrication process flow. The stacked MiT probes can also be realized in standard CMOS processes where the different metal layers can be used as the probe tips. Referring to FIG. 17 is an image of the finalized probe device according to the method of Table 7. The finalized probe comprises a first probe set 96 and a second probe set 98, the first probe set being vertically stacked compared to the second probe set.

TABLE 7 Fabrication Process for Vertically Stacked Monolithically Integrated Probe Tip Devices. Step # Process 700 Start with a DSP silicon wafer. 702 Deposit SiO₂ on both frontside and backside of wafer. 704 Pattern the SiO₂ layer with photoresist then etch the SiO₂ layer. 706 Strip the photoresist. 708 On the frontside of the wafer, sequentially deposit 1^(st) metal, SiO₂ and 2^(nd) metal layers. 710 Spin resist and pattern it. 712 Etch the 2^(nd) metal, SiO₂ and 1^(st) metal layers. 714 Strip the resist. 716 Use the backside SiO₂ layer as DRIE etch mask to etch the wafer. 718 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both the frontside and backside SiO₂ layers. The probe device is fully released at this stage.

EXAMPLE 8 Fabrication of Monolithically Integrated Fabrication of Monolithically Integrated Self-Aligned Stacked Probe Devices with Post Processed Probe Tip Configuration. Self-Aligned Stacked Probe Devices

Each MiT probe that makeup the vertically stacked monolithically integrated probe tip devices that was illustrated in Table 7 above have the same number of probe tips. In certain applications, a modified probe tip configuration might be required. In such situations, the FIB can be used to remove unneeded probe tips, as shown in Table 8. Removal of unneeded probe tips is not limited to the use of FIB but other means such as ion milling and reactive ion etching are possible. The metal choice used in the MiT probe stack could be the same (1^(st) metal the same as 2^(nd) metal) or different (1^(st) metal different from 2^(nd) metal). The MiT probe stack is not limited to two layers but several layers can also be implemented using the outlined fabrication process flow. Referring to FIG. 18 is an image of the finalized probe device according to the method of Table 8.

TABLE 8 Fabrication Process for Vertically Stacked Monolithically Integrated Probe Tip Devices with FIB-Modified Probe Tip Configuration. Step # Process 800 Start with DSP silicon wafer. 802 Deposit SiO₂ on both frontside and backside of wafer. 804 Pattern the SiO₂ layer with photoresist then etch the SiO₂ layer. 806 Strip the photoresist. 808 On the frontside of the wafer, sequentially deposit 1^(st) metal, SiO₂ and 2^(nd) metal layers. 810 Spin resist and pattern it. 812 Etch the 2^(nd) metal, SiO₂ and 1^(st) metal layers. 814 Strip the resist. 816 From the backside of the wafer, etch the Si wafer and SiO₂ layer on both the backside and the exposed part of the frontside. 818 Use the FIB to mill part of the 1^(st) metal of the middle probe tip. 820 Use the FIB to mill part of the 2^(nd) metal of the side tips. 822 Use either vapor HF or Buffered Oxide Etch (BOE) to etch the frontside SiO₂ layers. The probe device is fully released at this stage.

EXAMPLE 9 Fabrication of Monolithically Integrated Out-of-Plane Probe Tip Device

SRAM, DRAM and flash memory are typically arrayed and the plug spacing for the source, drain and gate are fixed. These plugs could be relatively easily accessed with MiT probes that have predefined tip configurations that directly address these specific plug layouts. The MiT probes can be designed specifically for a particular technology node and semiconductor foundry. The metal choice used for the probe tips in the MiT probe could be the same (1^(st) metal the same as 2^(nd) metal) or different (1^(st) metal different from 2^(nd) metal), as shown in Table 9. Referring to FIG. 19 is an image of the finalized probe device according to the method of Table 9.

TABLE 9 Fabrication Process for Out-of-Plane MiT Probe. Step # Process 900 Start with a DSP silicon wafer. 902 Deposit SiO₂ on both sides of the wafer. 904 Spin photoresist and pattern the backside of the wafer. Etch the backside SiO₂ layer. 906 Strip the photoresist. 908 Spin photoresist on the frontside and pattern the side probe tips. Reactive Ion Etching (RIE) halfway into the SiO₂ layer and strip the photoresist. 910 Sputter the 1^(st) metal layer on the frontside of the wafer. 912 Perform Chemical Mechanical Polishing (CMP) to planarize the frontside of wafer. 914 On the frontside of the wafer, sequentially deposit another SiO₂ layer followed by sputtering a 2^(nd) metal layer. The 1^(st) and 2^(nd) metal layers could be the same or different metals. 916 Spin resist and pattern it. 918 Etch 2^(nd) metal layer and frontside SiO₂ layer. Strip photoresist. 920 Use the backside SiO₂ layer as an etch mask to DRIE the wafer to the frontside SiO₂ layer. 922 Dry etch both the backside and frontside SiO₂ layers. 924 The side probe tips are embedded in the SiO₂ layer while the middle probe tip sits on a SiO₂ support layer.

EXAMPLE 10 Fabrication of Monolithically Integrated Freely Suspended Out-of-Plane Probe Tip Device

The out-of-plane MiT probe that was illustrated in Table 9 above had the middle probe tip fixed to the SiO₂ support layer. Table 10 below details out the fabrication of a fully suspended and movable out-of-plane middle probe tip device. Referring to FIG. 20 is an image of the finalized probe according to the method of Table 10.

TABLE 10 Process for Making Monolithically Integrated Freely Suspended Out-of-Plane MiT Probe Step # Process 1000 Start with DSP silicon wafer. 1002 Deposit SiO₂ on both sides of the wafer. 1004 Spin photoresist and pattern the backside of the wafer. Etch the backside SiO₂ layer. 1006 Strip the photoresist. 1008 Spin photoresist on the frontside and pattern the side probe tips. RIE halfway into the SiO₂ layer and strip the photoresist. 1010 Sputter the 1^(st) metal layer on the frontside of the wafer. 1012 Perform Chemical Mechanical Polishing (CMP) to planarize the frontside of wafer. 1014 On the frontside of the wafer, sequentially deposit another SiO₂ layer followed by sputtering a 2^(nd) metal layer. The 1^(st) and 2^(nd) metal layers could be the same or different metals. 1016 Spin resist and pattern it. 1018 Etch 2^(nd) metal layer and strip photoresist. 1020 Use the backside SiO₂ layer as an etch mask to DRIE the wafer to the frontside SiO₂ layer. 1022 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both the frontside and backside SiO₂ layers. The probe device is fully released at this stage.

According to an embodiment, various combinations of the different probe configurations (single tip, 2, 3 and/or 4-Tip MiT probes) can be simultaneously used to scan and nanoprobe. According to one example, a 3-Tip MiT probe could be utilized to access the source, drain, gate plugs of a transistor then bringing in an independent single tip device to probe the bulk (body) of the transistor.

Fabrication of Monolithically Integrated Freely Suspended Out-Of-Plane Probe Tip Device with Bottom and Side Actuation Electrodes

Bottom electrodes are used to deflect the probe tips up or down with respect to the substrate. But in certain applications, the side probe tips might need to be laterally deflected. For instance, when the gate length of two transistors varies, the side tips must be laterally deflected in order to access the source and drain plugs. Table 11 below illustrates the fabrication process flow for making MiT probes with side actuation electrodes. Referring to FIG. 21 is an image of the finalized probe device according to the method of Table 11.

TABLE 11 Fabrication Process Flow for Making Monolithically Integrated Freely Suspended Out-of-Plane MiT Probe with Side and Bottom Actuation Electrodes. Step # Process 1100 Start with undoped DSP silicon wafer. 1102 Deposit 2 μm of PECVD SiO₂ on one side of the DSP polished wafer. 1104 Pattern the SiO₂ layer with photoresist then etch the SiO₂ layer. 1106 Strip the photoresist 1108 Spin resist on frontside of the wafer. 1110 Pattern the bottom actuation electrodes. 1112 Using the resist as an etch mask, etch about 500 nm into the silicon wafer. Strip resist. 1114 Sputter about 1 μm of 1^(st) metal layer to fill-in the etched trenches. 1116 Perform Chemical Mechanical Polishing (CMP) to planarize the wafer surface. The bottom electrodes are embedded into the silicon wafer. 1118 Spin photoresist on the frontside and pattern the side probe tips. RIE halfway into the SiO₂ layer and strip the photoresist. 1120 Sputter the 1^(st) metal layer on the frontside of the wafer. 1122 Perform Chemical Mechanical Polishing (CMP) to planarize the frontside of wafer. 1124 On the frontside of the wafer, sequentially deposit another SiO₂ layer followed by sputtering a 2^(nd) metal layer. The 1^(st) and 2^(nd) metal layers could be the same or different metals. 1126 Spin resist and pattern it. 1128 Etch 2^(nd) metal layer and strip photoresist. 1130 Use the backside SiO₂ layer as an etch mask to DRIE the wafer to the frontside SiO₂ layer. 1132 Use either vapor HF or Buffered Oxide Etch (BOE) to etch both the frontside and backside SiO₂ layers. The probe device is fully released at this stage.

According to an embodiment, the lateral actuation electrodes for the side probe tips can be implemented for all the above MiT probe designs.

Implementation of Mobile Circuits with Multiple Integrated Tip Device.

The MiT probes can be used to implement various active and passive circuit components (transistor, resistor, diode and capacitor) on substrates. Since the MiT probe is capable of electrically mapping different regions of a substrate, at each spot, an active or passive component can be implemented on the substrate. Thus, these components are not lithographically fixed to the substrate but are mobile. For example, the 3-Tips MiT probe can be used to implement a transistor on a substrate. The middle probe tip represents the gate and the side probe tips are the source and drain terminals as shown in FIG. 22 . The side tips are in soft contact with the substrate whereas the middle probe tip can either be in soft contact (the tip has a dielectric coating) or proximity (air gap serves as the gate dielectric). At any location on the substrate, a transistor can be formed. Thus, both the output and transfer curves of a transistor can be mapped at each point on the surface of a substrate. The substrate could be a 2D material such as graphene, molybdenum disulphide, silicon substrate, GaN wafer substrate, etc.

Referring to FIG. 23 is the design of the 3-Tip MiT probe showing various actuation electrodes. FIGS. 24 and 25 show the tip design of the 3-Tip MiT probe and the gate capacitance between the middle probe tip and the substrate respectively. The middle tip is designed to be shorter than the side probe tips. The gate capacitance can be varied by applying DC voltages to electrode A2 which would retract or extend the middle probe tip. Thus, the effect of the gate capacitance on the transistor performance can be measured and investigated. FIG. 26 on the other hand shows a 3-Tip MiT probe which has a few nanometers of either high or low-k dielectric that is deposited at the apex of the middle probe tip. The dielectric layer serves as the gate oxide and the middle probe tip is aligned with the side probe tips.

A variable resistor on the other hand can be implemented by changing the spacing between the middle probe tip and any of the side tips. Applied voltages to C1 or C2 would laterally deflect the middle probe tip. By varying the tip spacing and contacting the substrate, different substrate resistance values can be achieved as demonstrated in FIGS. 27 and 28 .

Two or more active or passive circuit components that are implemented with two or more MiT probes can be cascaded to form various circuits such as common source amplifier, common gate amplifier, a source follower, etc. FIG. 29 shows the typical circuit configuration of a common source amplifier. This circuit could be implemented by at least a 3-Tip MiT probe and either a 2, 3, or 4-Tip MiT probe. As an example, two 3-Tip MiT probes where one of the MiT probes would implement the transistor and the other would implement the resistor. Or a 3-Tip MiT probe for the transistor and 2-Tips or 4-Tips MiT probe for the resistor.

While various embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, embodiments may be practiced otherwise than as specifically described and claimed. Embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

The above-described embodiments of the described subject matter can be implemented in any of numerous ways. For example, some embodiments may be implemented using hardware, software or a combination thereof. When any aspect of an embodiment is implemented at least in part in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single device or computer or distributed among multiple devices/computers. 

What is claimed is:
 1. A method for implementing a transistor using multiple integrated probe tips, the method comprising the steps of: providing a sample; providing a microscope probe comprising a plurality of probe tips; contacting a first outer probe tip of the plurality of probe tips to the sample, wherein the first outer probe tip is configured to act as a source terminal for a transistor; contacting a second outer probe tip of the plurality of probe tips to the sample, wherein the second outer probe tip is configured to act as a drain terminal for the transistor; using an inner probe tip of the plurality of probe tips as a gate terminal for the transistor; and characterizing the sample with the plurality of probe tips.
 2. The method of claim 1, wherein the inner probe tip makes soft contact with the sample.
 3. The method of claim 1, wherein the inner probe tip is in proximity to the sample.
 4. The method of claim 1, wherein the inner probe tip comprises a dielectric coating, and further wherein the dielectric coating is in contact with the sample.
 5. The method of claim 1, wherein the inner probe tip comprises a few nanometers of either high or low-k dielectric that is deposited at an apex of the inner probe tip.
 6. The method of claim 1, wherein the inner probe tip comprises a dielectric coating, and further wherein the dielectric coating is in proximity to the sample.
 7. The method of claim 1, wherein the sample comprises a 2D material.
 8. The method of claim 7, wherein the 2D material is graphene or molybdenum disulphide.
 9. The method of claim 1, wherein the sample comprises silicon substrate or gallium nitride.
 10. The method of claim 1, wherein the plurality of probe tips is used to perform output and transfer curves of the transistor.
 11. The method of claim 1, wherein the inner probe tip is configured to be shorter than both the first outer probe tip and the second outer probe tip.
 12. The method of claim 11, wherein there is an airgap or a gate capacitance between the inner probe tip and the sample.
 13. The method of claim 12, wherein the gate capacitance is varied by applying voltages to an actuation electrode that causes the inner probe to extend towards or retract from the sample. 